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LTC3219
OPERATION
Bus Speed
The I 2 C port is designed to be operated at speeds of up
to 400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I 2 C compliant master
device. It also contains input ?lters designed to suppress
glitches should the bus become corrupted.
Start and Stop Conditions
A bus-master signals the beginning of a communication
to a slave device by transmitting a Start condition.
A Start condition is generated by transitioning SDA from
high to low while SCL is high. When the master has
?nished communicating with the slave, it issues a Stop
condition by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I 2 C device.
Byte Format
Each byte sent to the LTC3219 must be eight bits long
followed by an extra clock cycle for the Acknowledge bit
to be returned by the LTC3219. The data should be sent
to the LTC3219 most signi?cant bit (MSB) ?rst.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active Low)
generated by the slave (LTC3219) lets the master know
that the latest byte of information was received. The
Acknowledge related clock pulse is generated by the
master. The master releases the SDA line (High) during
the Acknowledge clock cycle. The slave-receiver must pull
down the SDA line during the Acknowledge clock pulse
so that it remains a stable Low during the High period of
this clock pulse.
Slave Address
The LTC3219 responds to only one 7-bit address which
has been factory programmed to 0011011. The eighth
bit of the address byte (R/W) must be 0 for the LTC3219
to recognize the address since it is a write only device.
This effectively forces the address to be eight bits long
where the least signi?cant bit of the address is 0. If the
correct seven bit address is given but the R/W bit is 1,
the LTC3219 will not respond.
Bus Write Operation
The master initiates communication with the LTC3219
with a START condition and a 7-bit address followed
by the Write Bit R/W = 0. If the address matches that
of the LTC3219, the LTC3219 returns an Acknowledge.
The master should then deliver the most signi?cant
sub-address byte for the data register to be written.
Again the LTC3219 acknowledges and then the data is
delivered starting with the most signi?cant bit. This cycle
is repeated until all of the required data registers have
been written. Any number of data latches can be written.
Each data byte is transferred to an internal holding latch
upon the return of an Acknowledge. After all data bytes
have been transferred to the LTC3219, the master may
terminate the communication with a Stop condition.
Alternatively, a Repeat-Start condition can be initiated
by the master and another chip on the I 2 C bus can be
addressed. This cycle can continue inde?nitely and the
LTC3219 will remember the last input of valid data that it
received. Once all chips on the bus have been addressed
and sent valid data, a global Stop condition can be sent
and the LTC3219 will update all registers with the data
that it had received.
In certain circumstances the data on the I 2 C bus may
become corrupted. In these cases the LTC3219 responds
appropriately by preserving only the last set of complete
data that it has received. For example, assume the LTC3219
has been successfully addressed and is receiving data
when a Stop condition mistakenly occurs. The LTC3219
will ignore this stop condition and will not respond until
a new Start condition, correct address, sub-address and
new set of data and Stop condition are transmitted.
Likewise, if the LTC3219 was previously addressed and
sent valid data but not updated with a Stop, it will respond
3219fa
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